Title: Final
Course: Digital Fundamentals (IC 103-IC 103) > Section: Assessments

Q: A logic circuit that provides a High output for both inputs High or both inputs Low is a(n).
- XNOR gate
- OR gate
- XOR gate
- NAND gate
A: XNOR gate

Q: A negative-edge triggered J-K flip-flop will Set (Q=1) when _______________.
- the J input is 1, the K input is 0, and the clock is High
- the J input is 1, the K input is 0, and the clock is Low
- The J input is 1, the K input is 0, and the clock transitions from Low to High
- the J input is 1, the K input is 0, and the clock transitions from High to Low
A: the J input is 1, the K input is 0, and the clock is High

Q: An AND gate with schematic "bubbles" on its inputs preforms the same function as a(n) _________ gate.
- NOT
- NOR
- OR
- NAND
A: NOT

Q: Convert binary 111111110010 to hexadecimal.
- EE2
- 2FE
- FF2
- FD2
A: EE2

Q: Convert hexadecimal value 16 to decimal.
- 22
- 10
- 16
- 20
A: 22

Q: Convert the following binary number 001101011 to Octal.
- 153
- 253
- 351
- 352
A: 153

Q: Convert the following decimal number 187 to binary.
- 10111011
- 10111101
- 11011101
- 10111100
A: 10111011

Q: Covert the following binary number 01011 to decimal.
- 11
- 35
- 15
- 10
A: 11

Q: How is a J-K flip-flop made to toggle?
- J=0, K=0
- J=1, K=0
- J=0, K=1
- J=1, K=1
A: J=0, K=0

Q: If a 2-input NOR gate has four input possibilities, how many of those possibilities will result in a High (1) output?
- 1
- 2
- 3
- 4
A: 1

Q: If an active-High S-R latch has a 0 on the S input and a 1 on the R input, the latch will be ___________.
- set
- reset
- invalid
A: set

Q: Convert the following binary number 10011010 to decimal.
- 153
- 157
- 154
- 155
A: 153

Q: Convert hexadecimal value C1 to binary.
- 1000111
- 111000100
- 111000001
- 11000001
A: 1000111

Q: The Boolean expression for a 2-input OR gate is _________.
- X=AB
- X=A+B
- X=AxB
A: X=AB

Q: The format used to represent the logic output for the various combinations of logic inputs to a gate is called a (n):
- Boolean constant
- Boolean variable
- truth table
- input logic function
A: Boolean constant

Q: The output of a NOR gate is High if ____________.
- all inputs are High
- any input is High
- any input is Low
- All inputs are Low
A: all inputs are High

Q: The output of a NOT gate is High when ________.
- the input is Low
- the input is High
- power is applied to the gate
- power is removed from the gate
A: the input is Low

Q: The output of an AND gate with two inputs (A and B), is High (1) when __________.
- A=1, B=1
- A=0, B=0
- A=1, B=0
- A=0, B=1
A: A=1, B=1

Q: The output of an OR gate with two inputs (A and B), is Low (0) when ___________.
- A=1, B=1
- A=1, B=0
- A=0, B=1
- A=0, B=0
A: A=1, B=1

Q: The symbol on the clock terminal of this flip-flop indicates _______________.
- triggering takes place on the negative-going edge of the clock pulse
- triggering takes place on the positive-going edge of the clock pulse
- triggering can take place anytime during the high level of the clock waveform
- triggering can take place anytime during the Low level of the clock waveform
A: triggering takes place on the negative-going edge of the clock pulse

Q: What does the small bubble on the output of the NAND gate logic symbol mean?
- open collector output
- tristate
- the output is inverted
A: open collector output

Q: What does the triangle on the clock input of a J-K flip-flop mean?
- level enabled
- edge triggered
A: level enabled

Q: What is one disadvantage of an S-R flip-flop?
- it has no enable input
- it has an invalid state
- it has no clock input
- it has only a single output
A: it has no enable input

Q: What is the No Change (Hold) condition of a flip-flop?
- both S and R inputs are activated (1)
- both S and R inputs are not activated (0)
- only S is active (1)
- only R is active (1)
A: both S and R inputs are activated (1)

Q: Which one of the following logical operations (gates) is represented by the + sign in Boolean algebra?
- inversion
- AND
- OR
- complementation
A: inversion